Mr. Mukesh Kumar Sukla

Education

Work Experience

Research Interests

• Memory Design
• VLSI

Publications

1. M Suresh, Ajit Kumar Panda, Mukesh Kumar Sukla, Jayshree Acharya, Lusita Sahu . M. Suresh, Ajit Kumar Panda, “Power Analysis and Simulation of Low Power Gated-Clock Design of LFSR using 250nm Technology”, International Journal of Computational Intelligence Research and Applications”, Vol. 3, No. 1, January – June 2009, pp. 157-161, ISSN: 0973-6794.
2. M Suresh, Mukesh K Sukla, A K Panda, “Performance Analysis of Multiplexer using Low Power Techniques ”, Indian Journal of Scientific Research, 17(2):65 – 73, 2018, ISSN: 0976 – 2876(Print), ISSN: 2250-0138(online).
3. International Conference on VLSI and Communication 2009 (ICVCom-09), SAINTGITS College of Engineering, KERALA.
4. 11th IEEE VLSI Design And Test Symposium held at Saha Institute of Radio Physics, Kolkata during August 8-10, 2007.
5. Cadence User’s Conference “CDN Live – 2018” organized by CADENCE PVT. LTD. at Park Plaza, Bangalore on 06th and 7th September, 2018
6. Participated in the 21st International Symposium on VLSI Design and Test (VDAT-2017) held at Department of Electronics and Communication Engineering, IIT-Roorkee during 29th June – 2nd July. 2017.
7. Participated in 6th Annual Conference of Telemedicine Society of India (TSI), Odisha Chapter (ODITELECON-2017) held on 9th April, 2017 at NIST-Berhampur.
8. Attended Cadence University Conference “ Architecture to Silicon to System: Academia’s Role in Electronic Design and R&D” held on December 06, 2016 at Bangalore.
9. Cadence User’s Conference “CDN Live – 2015” organized by CADENCE PVT. LTD. at Park Plaza, Bangalore on 18th and 19th August, 2015.
10. 19th International Symposium on VLSI Design and Test (VDAT 2015), 26TH – 29TH June, 2015 organized by VLSI Society of India and Institute of Technology, Nirma University, Ahmedabad.
11. 17th International Symposium on VLSI Design And Test (VDAT 2013) from July 27 – 30, 2013 at Malaviya National Institute of Technology, Jaipur, INDIA.
12. National Conference on VLSI Design & Embedded Systems (NCVDES – 2011), organized by IETE – Pilani Centre in association with CSIR – CEERI, Pilani, BITS – Pilani, Pilani and BKBIET, Pilani at CSIR – CEERI Pilani, Rajasthan, October 12 – 14, 2011.
13. IEEE EDS Mini-Colloquium on “Nano Electronics” organized by National Institute of Science and Technology, Berhampur, Odisha on 30th December, 2010.
14. Mukesh Kumar Sukla, Shasanka Sekhar Rout, Sunil Kumar Behera, “Design of Low Power Analog Multiplexer for Sensor Interfacing” 5th National Conference on Devices and Circuits, 2nd March, 2019, ISBN: 978-93-83060-12-2, PP. 62 - 66.
15. Manoja Kumar Senapati, Mukesh Kumar Sukla, Subhadeepta Tripathy, Rohit Padhy, “Design and Implementation 8-bit soft-core Microcontroller on FPGA” 4th National Conference on Devices and Circuits, 24th February, 2018, ISBN: 978-93-83060-16-0, PP. 86 – 91.
16. Abinash Ku Pala, M Suresh, Ajit Ku Panda, Mukesh Ku Sukla, “Efficient Design of 4X4 Vedic Multiplier” 3rd National Conference on Devices and Circuits, 7th March, 2017, ISBN: 978-93-83060-18-4, PP. 115 – 118.
17. Mukesh Kumar Sukla, M Suresh, “Design of GDI & Hybrid Adder in Error Tolerant Multiplier for Low Power, High Speed DSP Applications” 2nd National Conference on Devices and Circuits, 19th February, 2016, ISBN: 978-93-82208-78-5, PP. 93 - 97.
18. Niteesh Kumar, Lalit Mohan Upadhyay, M K Sukla, “Physical Design and Verification of High Precision Sense Amplifier for RAM”, 1st National Conference on Devices and Circuits, 21st February, 2015, ISBN: 978-93-82208-75-4, PP. 118 - 121.
19. Spandana Gannavarapu, Shyama Nayak, M K Sukla, “Implementation and Verification of I2C Protocol”, 1st National Conference on Devices and Circuits, 21st February, 2015, ISBN: 978-93-82208-75-4, PP. 67 - 69.
20. Reetish Pattnayak, Rakesh Sahu, M K Sukla, “Power Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers”, 1st National Conference on Devices and Circuits, 21st February, 2015, ISBN: 978-93-82208-75-4, PP. 104 - 107.
21. Mithun Kumar Swain, Mukesh Kumar Sukla, “Design and Implementation of Fast Carry FA for DSP Applications”, 1st National Conference on Devices and Circuits, 21st February, 2015, ISBN: 978-93-82208-75-4, PP. 113 - 117.
22. Meraj Saheel, M. Suresh, A K Panda, M K Sukla, “Design of Reversible Logic Gates Using 0.12µm Technology”, 1ST National Conference on Electronics Communication & Instrumentation”, e-Marathon 2 – 3 April, 2010.
23. M Suresh, Ajit Kumar Panda, M K Sukla, Madhusmita Mahapatra, Sisira Kanta Panda, Jagannath Satapathy, Meraj Saheel, “Design of Arithmetic Circuits using Reversible Logic Gates and Power Dissipation Calculation ”, International Symposium on Electronic System Design, 978-0-7695-4294-2/10, 2010 IEEE, pp. 85 – 90.
24. Three Day Workshop on “VLSI and Embedded System Design (VESD-2017)” on 13th – 15th October 2017 at the School of Electrical Sciences, IIT-Bhubaneswar, Odisha, INDIA.
25. Two Days workshop on Innovative Research in Pedagogy for Mini-MOOCs Blended with Instruction Strategies to enhance quality of higher education held on 19th – 20th August, 2017 at NIST-Berhampur in collaboration with Thapar University, Patiala.
26. Tutorial Session in the 21st International Symposium on VLSI Design and Test (VDAT-2017) held at Department of Electronics and Communication Engineering, IIT-Roorkee during 29th June 2017.
27. Participated in a Two-Weeks ISTE STTP on CMOS, Mixed Signal and Radio Frequency VLSI Design conducted by IIT-Kharagpur from 30th January to 4th February, 2017 held under the National Mission on Education through ICT (MHRD) at NIST Berhampur (Nodal Center)
28. A Short term course on VLSI Digital Signal Processing Architecture (VDSPA-2017) at School of Electrical Sciences, IIT-Bhubaneswar during 2nd – 6th January, 2017.
29. Attended an FDP on ASIC Verification by MAVEN SILICON, Bangalore on 3rd – 4th September, 2016
30. Attended Workshop on CADENCE and ANYSYS HFSS TOOL TRAINING conducted by Biju Patnaik University of Technology, Odisha at CET Bhubaneswar during 1st – 5th February, 2016.
31. One day tutorial “SCL 180nm CMOS Foundry: High Reliability ASIC Design for Aerospace Applications” at 19th International Symposium on VLSI Design and Test, VDAT 2015 jointly organized by VLSI Society of India and Institute of Technology, Nirma University, Ahmedabad.
32. One day workshop “Cadence VLSI Design Tools” at 19th International Symposium on VLSI Design and Test, VDAT 2015 jointly organized by VLSI Society of India and Institute of Technology, Nirma University, Ahmedabad.
33. Attended the National Workshop on Embedded Design Flow using XILINX ZYNQ SOC organized by IEEE ED-NIST Student Chapter at NIST-Berhampur in association with CoreEL Technologies and XILINX on 9th – 10th April, 2015.
34. Two weeks workshop on “Real Time Embedded System Design for Signal Processing Application – An FPGA Design Approach” jointly organized by IEEE EDS NIST Students Chapter and National Institute of Science and Technology, Berhampur, Odisha from 12th – 23rd July, 2013.
35. Two week ISTE Workshop on “Analog Electronics” conducted by Indian Institute of Technology, Kharagpur from 4th – 14th June, 2013 under the National Mission on Education Though ICT (MHRD).
36. 1ST Industry Academia Workshop on 11TH and 12TH January 2013 at BVB College of Engineering and Technology, Hubli.
37. Attended Mission 10X workshop conducted at National Institute of Science and Technology at Berhampur from 20th July to 24th July 2010.
38. Attended a workshop on High Impact Teaching Skills by Dale Carnegie & Associates, Inc. Trainer and WIPRO on 20th and 21st, 2010.
39. Attended an intensive AICTE Sponsored Faculty Development Program on MICROELECTRONICS/ VLSI DESIGN FOR ENGINEERS AND SCIENTISTS conducted by National Institute of Science and Technology, Berhampur during 27th July – 8th August, 2009.
40. Attended AICTE sponsored Faculty Development Program on Advanced Computer Control Of Industrial Process & Automation Engineering held during 6th – 11th July, 2009 at NIST-Berhampur.
41. Real-Time Issues on Power Engineering” organized by NIST, Berhampur, Odisha on 11th December 2007.
42. Workshop On Embedded System & DSP-in-VLSI” conducted at NIT, Rourkela during 5th -6th December 2007.
43. One Day Seminar on VLSI Design Using Tanner Tool at NIST, Berhampur on 5th November 2007.