NIST UNIVERSITY
Institute Park, Berhampur, Odisha-761008, India

Arttatran Sahu

Mr. Arttatran Sahu

Assistant Professor

Electronics and Comm. Engineering (SCHOOL OF ENGINEERING)

arttatran@nist.edu
-

Education

M.Tech in VLSI and Embedded Systems Design
National Institute of Science and Technology,Berhampur
2016
B.Tech in Electronics and Communication Engineering
National Institute of Science and Technology,Berhampur
2012

Work Experience

Asst. professor
National Institute of Science and Technology,Berhampur

Research Interests

  • VLSI Design
  • Quantum semiconductor structures
  • Transport in Coupled Quantum wells

Publications

  1. Nonlinear electron transport in GaAs/InGaAs asymmetric double-quantum-wellpseudomorphic high-electron-mobility transistor structure, Japanese Journal of Applied Physics 56, 064101 (2017),Meryleen Mohapatra, Arttatran Sahu, Sangita R. Panda, Sudhakar Das, Trinath Sahu, and Ajit K. Panda.
  2. Effect of spacer width on Electron Mobility in Single Side Barrier Delta-Doped AlGaAs/GaAs Single Quantum Well Structure, IEEE Proceedings of 3rd NCDC, ISBN : 978-93-83060-18-4 (2017), Sangita Rani Panda, Arttatran Sahu, Sudhakar Das, Trinath Sahu & Ajit Kumar Panda.
  3. Effect of Structure Parameter Variations on Electron Mobility in Barrier Delata-Doped AlGaAs/GaAs Single Quantum Well Structures, IEEE Proceedings of 2rd NCDC, ISBN : 978-93-82208-78-5 (2016), Arttatran Sahu, Sudhakar Das, Trinath Sahu & Ajit Kumar Panda.
  4. ISTE workshop of 2 weeks on "Analog Electronics" held at NIST, Berhampur,collaborating withIIT, Kharagpur, June 2013.
  5. IEEE EDS Student Chapter workshop of 2 weeks on "Real Time Embedded System Design for Signal Processing Applicaion - An FPGA Design Approach" held at NIST, Berhampur, July 2013.
  6. "VLSI System Design" held at NIST, Berhampur collaborating withNITTTR, Chandigarh, Nov 2014.
  7. "Advanced Embedded System Design on ZYNQ using Vivado targeting Zed Board" held at NIT, Trichy, Aug 2015.
  8. "2nd National Conference on Devices and Circuits" held at NIST, Berhampur, Feb 2016.
  9. ISTE workshop of one week on "CMOS, Mixed Signal and Radio Frequency VLSI Design" held at NIST, Berhampur, collaborating with IIT, Kharagpur, Jan-feb 2017.
  10. "MODELING and SIMULATION of NANO-TRANSISTORS" held at IIT, Kanpur, Feb 2017.
  11. "3rd National Conference on Devices and Circuits" held at NIST, Berhampur, Mar 2017.