NIST UNIVERSITY
Institute Park, Berhampur, Odisha-761008, India

Priyadarsan Patra

Dr. Priyadarsan Patra

Vice Chancellor

Computer Science and Engineering (SCHOOL OF ENGINEERING)

vc@nist.edu
2492421
ATR - 513

Education

Ph.D in Computer Science
The University Of Texas at Austin
05/06/1995
M.Sc in Computer and Information Science
University of Massachusetts Amheerst
B.Engg in Electronics and Telecommunication Engineering
IISc Bangalore

Work Experience

Dean of Computer Sciences and Advisor to the VC
University of Petroleum and Energy Studies
Senior Tech Prinicipal & Chief Validation Architect
Intel Corporation
Xavier University BBSR
Xavier University
Pro Vice-chancellor and Distinguished Professor
DIT University
01/10/2021 - 26/09/2024
Vice-chancellor
NIST University
26/09/2024 - 01/03/2026

Research Interests

  • Leadership, VLSI, System Architecture

Publications

  1. Patra, P., 2007. On the cusp of a validation wall. IEEE Design & Test of Computers, 24(2), pp.193-196.
  2. Patra, P., 1995. Approaches to design of circuits for low-power computation. The University of Texas at Austin.
  3. Li, B., Peh, L.S. and Patra, P., 2008, April. Impact of process and temperature variations on network-on-chip design exploration. In Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) (pp. 117-126). IEEE.
  4. Mondal, B., Patra, O., Mishra, S. and Patra, P., 2020, March. A course recommendation system based on grades. In 2020 international conference on computer science, engineering and applications (ICCSEA) (pp. 1-5). IEEE.
  5. Chen, K., Malik, S. and Patra, P., 2008, February. Runtime validation of memory ordering using constraint graph checking. In 2008 IEEE 14th International Symposium on High Performance Computer Architecture (pp. 415-426). IEEE.
  6. Patra, P., Polonsky, S. and Fussell, D.S., 1997, April. Delay insensitive logic for RSFQ superconductor technology. In Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (pp. 42-53). IEEE.
  7. Mandal, M., Sahoo, S.K., Patra, P., Mallik, S. and Zhao, Z., 2020. In silico ranking of phenolics for therapeutic effectiveness on cancer stem cells. BMC bioinformatics, 21(Suppl 21), p.499.
  8. Dike, C.E., Kurd, N.A., Patra, P. and Barkatullah, J., 2003, June. A design for digital, dynamic clock deskew. In 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No. 03CH37408) (pp. 21-24). IEEE.
  9. Basu, K., Mishra, P. and Patra, P., 2011, September. Efficient combination of trace and scan signals for post silicon validation and debug. In 2011 IEEE International Test Conference (pp. 1-8). IEEE.
  10. Patra, P., From parallel programs to asynchronous VLSI. tech. rep., Dept. of Computer Sciences, The Univ of Texas at Austin, 1991. Appears in report collection CS-TR-91-18.
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