Course Highlights:

• World class curriculum - enables graduates to be “industry-ready”
• Leverage best-in-class Cadence technologies and access to ecosystem partners
• Provide an incremental training approach leading up from VLSI basics to industry-relevant skills
• More than 200 hours of Theory + Labs + Tool Training
• Course can run on weekend also

Course Details:

General Courses: Introduction to the Linux Operating systems, Scripting, Editing
Digital Courses: Theory + Labs + Tool Training
Implement, practical digital functional blocks using the Verilog language Coding HDL, Modeling HDL, RTL and gate level verification/simulation, creating timing constraints and running RTL synthesis, testing and Design for Testability (DFT), and top- down design methodology

Analog Courses: Theory + Labs + Tool Training
Introduction to practical working knowledge of the fundamental design and techniques Create and edit schematics for use with the suite of Cadence simulation and layout tools Verilog in and Spice in translators to generate netlists and symbols Place instances, wire schematics, use hierarchical design, run netlist creation and simulation, add rules using the Constraint Editor, create inherited connections, and generate layout instances from the schematicts

Soft Skills Training:: Interview, Communication, Presentation and Term Interaction skills

NB: Students will be trained to participate in Cadence Design Contest and there is a chance to win prize worth of Rs.1.5 Lakhs

Course Fees:

For Students: Rs.12,000/-
For Industry sponsored candidates: Rs. 15,000/-